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[X86] Make v2i1 and v4i1 legal types without VLX
authorCraig Topper <craig.topper@intel.com>
Sun, 7 Jan 2018 18:20:37 +0000 (18:20 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 7 Jan 2018 18:20:37 +0000 (18:20 +0000)
commit1184a94abb6ad738196b6aa4dd0e4198581306ec
tree68eb7d020db24ef500d344b155f64d92b7491ab0
parentf0c5b1c6c7933acb7ec3e5503f57595656a6408c
[X86] Make v2i1 and v4i1 legal types without VLX

Summary:
There are few oddities that occur due to v1i1, v8i1, v16i1 being legal without v2i1 and v4i1 being legal when we don't have VLX. Particularly during legalization of v2i32/v4i32/v2i64/v4i64 masked gather/scatter/load/store. We end up promoting the mask argument to these during type legalization and then have to widen the promoted type to v8iX/v16iX and truncate it to get the element size back down to v8i1/v16i1 to use a 512-bit operation. Since need to fill the upper bits of the mask we have to fill with 0s at the promoted type.

It would be better if we could just have the v2i1/v4i1 types as legal so they don't undergo any promotion. Then we can just widen with 0s directly in a k register. There are no real v4i1/v2i1 instructions anyway. Everything is done on a larger register anyway.

This also fixes an issue that we couldn't implement a masked vextractf32x4 from zmm to xmm properly.

We now have to support widening more compares to 512-bit to get a mask result out so new tablegen patterns got added.

I had to hack the legalizer for widening the operand of a setcc a bit so it didn't try create a setcc returning v4i32, extract from it, then try to promote it using a sign extend to v2i1. Now we create the setcc with v4i1 if the original setcc's result type is v2i1. Then extract that and don't sign extend it at all.

There's definitely room for improvement with some follow up patches.

Reviewers: RKSimon, zvi, guyblank

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41560

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321967 91177308-0d34-0410-b5e6-96231b3b80d8
23 files changed:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrVecCompiler.td
test/Analysis/CostModel/X86/cast.ll
test/CodeGen/X86/avx512-cvt.ll
test/CodeGen/X86/avx512-ext.ll
test/CodeGen/X86/avx512-insert-extract.ll
test/CodeGen/X86/avx512-intrinsics-upgrade.ll
test/CodeGen/X86/avx512-mask-op.ll
test/CodeGen/X86/avx512-vec-cmp.ll
test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll
test/CodeGen/X86/avx512vl-vec-cmp.ll
test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
test/CodeGen/X86/compress_expand.ll
test/CodeGen/X86/masked_gather_scatter.ll
test/CodeGen/X86/masked_memop.ll
test/CodeGen/X86/pr33349.ll
test/CodeGen/X86/sse-fsignum.ll
test/CodeGen/X86/vector-shuffle-v1.ll
test/CodeGen/X86/vselect-pcmp.ll