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[SelectionDAG] computeKnownBits - support constant pool values from target
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 24 May 2019 10:03:11 +0000 (10:03 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 24 May 2019 10:03:11 +0000 (10:03 +0000)
commit128852a784fc6b70dc5c719f41960d5835f40740
tree7844b3fb105678e7eb897de0fd04974212bf1cd4
parent85b221a6c24d8a14a41f181b56e072f31ebbc78e
[SelectionDAG] computeKnownBits - support constant pool values from target

This patch adds the overridable TargetLowering::getTargetConstantFromLoad function which allows targets to return any constant value loaded by a LoadSDNode node - only X86 makes use of this so far but everything should be in place for other targets.

computeKnownBits then uses this function to improve codegen, notably vector code after legalization.

A future commit will do the same for ComputeNumSignBits but computeKnownBits sees the bigger benefit.

This required a couple of fixes:
* SimplifyDemandedBits must early-out for getTargetConstantFromLoad cases to prevent infinite loops of constant regeneration (similar to what we already do for BUILD_VECTOR).
* Fix a DAGCombiner::visitTRUNCATE issue as we had trunc(shl(v8i32),v8i16) <-> shl(trunc(v8i16),v8i32) infinite loops after legalization on AVX512 targets.

Differential Revision: https://reviews.llvm.org/D61887

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361620 91177308-0d34-0410-b5e6-96231b3b80d8
17 files changed:
include/llvm/CodeGen/TargetLowering.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/TargetLowering.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
test/CodeGen/X86/avx512-vec-cmp.ll
test/CodeGen/X86/bitreverse.ll
test/CodeGen/X86/combine-bitreverse.ll
test/CodeGen/X86/combine-shl.ll
test/CodeGen/X86/movmsk-cmp.ll
test/CodeGen/X86/vector-bitreverse.ll
test/CodeGen/X86/vector-pcmp.ll
test/CodeGen/X86/vector-reduce-mul-widen.ll
test/CodeGen/X86/vector-reduce-mul.ll
test/CodeGen/X86/vector-shift-lshr-sub128.ll
test/CodeGen/X86/vector-zext.ll