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drm/i915: Simplify the DG1 power well descriptors
authorImre Deak <imre.deak@intel.com>
Thu, 14 Apr 2022 21:06:51 +0000 (00:06 +0300)
committerImre Deak <imre.deak@intel.com>
Wed, 20 Apr 2022 17:42:12 +0000 (20:42 +0300)
commit13344a9bdd38a8938dad385521ce601cecf4f4f7
treec180801ab611465813bc66fc05ddb6a219dbdb92
parenta6394dbbe21e5966e688dde24cc8fa5d0b44b346
drm/i915: Simplify the DG1 power well descriptors

Simplify the definition of DG1 power wells by reusing the identical
RKL DDI/AUX descriptors.

This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't
make a difference (it is the order on RKL and the DDI/AUX power wells
don't have a dependency on PW4/5).

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414210657.1785773-12-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display_power_map.c