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RISC-V: Adding XTheadSync ISA extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Tue, 31 Jan 2023 20:20:01 +0000 (21:20 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 6 Feb 2023 22:19:23 +0000 (08:19 +1000)
commit134c3ffa34d005861f37cf6258b09df229e7be22
tree7e9f894ca384c8d3abfeb66ef615fcac6255fe62
parent49a7f3aabba99e06768cbaf6c9429f514a9c7444
RISC-V: Adding XTheadSync ISA extension

This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.

The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/helper.h
target/riscv/insn_trans/trans_xthead.c.inc
target/riscv/op_helper.c
target/riscv/translate.c
target/riscv/xthead.decode