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clk: xgene: Fix divider with non-zero shift value
authorLoc Ho <lho@apm.com>
Thu, 19 Nov 2015 19:20:30 +0000 (12:20 -0700)
committerStephen Boyd <sboyd@codeaurora.org>
Fri, 20 Nov 2015 18:49:14 +0000 (10:49 -0800)
commit1382ea631ddddb634850a3795527db0feeff5aaf
tree72faaf0a0f6028d55cabcc7f4a4d9166c937849etree | snapshot
parent6dc669a22c77ad9c812bef82e186b3ab254470cbcommit | diff
clk: xgene: Fix divider with non-zero shift value

The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-xgene.c diff | blob | history
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