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drm/dsi: transfer DSI HS packets ending at the same time
authorRex-BC Chen <rex-bc.chen@mediatek.com>
Wed, 9 Mar 2022 07:36:35 +0000 (15:36 +0800)
committerRobert Foss <robert.foss@linaro.org>
Wed, 9 Mar 2022 13:14:36 +0000 (14:14 +0100)
commit1498915233dde830061e008ad639b482fd76f93d
tree09d4aee61b4e25fbed8c684266a48f3522449b67
parentdf0a9e8d3008050f61241f471c70438ef1e90a1b
drm/dsi: transfer DSI HS packets ending at the same time

Since a HS transmission is composed of an arbitrary number
of bytes that may not be an integer multiple of lanes, some
lanes may run out of data before others.
(Defined in 6.1.3 of mipi_DSI_specification_v.01-02-00)

However, for some DSI RX devices (for example, anx7625),
there is a limitation that packet number should be the same
on all DSI lanes. In other words, they need to end a HS at
the same time.

Because this limitation is for some specific DSI RX devices,
it is more reasonable to put the enable control in these
DSI RX drivers. If DSI TX driver knows the information,
they can adjust the setting for this situation.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309073637.3591-2-rex-bc.chen@mediatek.com
include/drm/drm_mipi_dsi.h