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target/riscv: change the api for RVF/RVD fmin/fmax
authorChih-Min Chao <chihmin.chao@sifive.com>
Thu, 21 Oct 2021 16:08:46 +0000 (00:08 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 29 Oct 2021 06:56:12 +0000 (16:56 +1000)
commit15161e425ee1bb1180f9cec574cda44fb10c0931
tree9c90b47ae53fcb338a122b1590b6c316e4074410
parent0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92
target/riscv: change the api for RVF/RVD fmin/fmax

The sNaN propagation behavior has been changed since cd20cee7 in
https://github.com/riscv/riscv-isa-manual.

In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with
IEEE 754-2008 minNum and maxNum operations.

In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to
implement IEEE 754-2019 minimumNumber and maximumNumber operations.

Therefore, to prevent the risk of having too many version variables.
Instead of introducing an extra *fext_ver* variable, we tie RVF version
to Priv version. Though it's not completely accurate but is close enough.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/fpu_helper.c