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MIPS: SEAD3: Disable L2 cache on SEAD-3.
authorSteven J. Hill <Steven.Hill@imgtec.com>
Thu, 27 Jun 2013 15:27:59 +0000 (15:27 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 1 Jul 2013 13:10:59 +0000 (15:10 +0200)
commit1535ac096d26538888d00881f5026cbc8b6dc20d
tree67b50a0a5982fc11be0d6b54db5b45d79dc217c8tree | snapshot
parent7ac836ce2aa7b931f6347e554cb65f9e9cc1da57commit | diff
MIPS: SEAD3: Disable L2 cache on SEAD-3.

The cores used on the SEAD-3 platform do not have L2 caches, so
this option should not be turned on. Originally fixed on public
'linux-mti-3.8' release branch.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5559/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/Kconfig diff | blob | history
Mirror: https://github.com/0ranko0P/kernel_xiaomi_msm8998/
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