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[DAGCombine] Improve ReduceLoadWidth for SRL
authorSam Parker <sam.parker@arm.com>
Thu, 21 Dec 2017 12:55:04 +0000 (12:55 +0000)
committerSam Parker <sam.parker@arm.com>
Thu, 21 Dec 2017 12:55:04 +0000 (12:55 +0000)
commit153f2e3851101517bf9e83a6b3bd7a52329bb4b7
treeab6e4d28d717ad5390e19a0b3e79602b71facb73tree | snapshot
parent2a379e0e2730b7209693f587d7039b44c1323453commit | diff
[DAGCombine] Improve ReduceLoadWidth for SRL

If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.

Differential Revision: https://reviews.llvm.org/D41350

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321259 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
test/CodeGen/ARM/shift-combine.ll diff | blob | history
test/CodeGen/X86/h-registers-1.ll diff | blob | history
external/llvm
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