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MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
authorHuacai Chen <chenhc@lemote.com>
Thu, 16 Mar 2017 13:00:28 +0000 (21:00 +0800)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 10 Apr 2017 09:56:08 +0000 (11:56 +0200)
commit17c99d9421695a0e0de18bf1e7091d859e20ec1d
treeb85ec6aa09ba082e12840be02bc2ea09fda28071
parent294d62743754f1fefefccccb09f8deec48f00969
MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/Kconfig