target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>