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New OptimizationRemarkEmitter pass for MIR
authorAdam Nemet <anemet@apple.com>
Wed, 25 Jan 2017 23:20:33 +0000 (23:20 +0000)
committerAdam Nemet <anemet@apple.com>
Wed, 25 Jan 2017 23:20:33 +0000 (23:20 +0000)
commit19925fc03b8400587d69bdbcd7186deb7b04ead5
treeb4f63793cf1677f9105138c67b6408e49bc38a3a
parent2355a8bd5e9fb36cc725eca7756e94c3924318db
New OptimizationRemarkEmitter pass for MIR

This allows MIR passes to emit optimization remarks with the same level
of functionality that is available to IR passes.

It also hooks up the greedy register allocator to report spills.  This
allows for interesting use cases like increasing interleaving on a loop
until spilling of registers is observed.

I still need to experiment whether reporting every spill scales but this
demonstrates for now that the functionality works from llc
using -pass-remarks*=<pass>.

Differential Revision: https://reviews.llvm.org/D29004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293110 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
include/llvm/Analysis/OptimizationDiagnosticInfo.h
include/llvm/CodeGen/MachineLoopInfo.h
include/llvm/CodeGen/MachineOptimizationRemarkEmitter.h [new file with mode: 0644]
include/llvm/IR/DiagnosticInfo.h
include/llvm/InitializePasses.h
lib/Analysis/OptimizationDiagnosticInfo.cpp
lib/CodeGen/CMakeLists.txt
lib/CodeGen/MachineLoopInfo.cpp
lib/CodeGen/MachineOptimizationRemarkEmitter.cpp [new file with mode: 0644]
lib/CodeGen/RegAllocGreedy.cpp
lib/IR/DiagnosticInfo.cpp
test/CodeGen/AArch64/arm64-spill-remarks.ll [new file with mode: 0644]
tools/llc/llc.cpp