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author	Vincent Chen <vincent.chen@sifive.com>
	Mon, 22 Mar 2021 14:26:04 +0000 (22:26 +0800)
committer	Palmer Dabbelt <palmerdabbelt@google.com>
	Mon, 26 Apr 2021 15:24:56 +0000 (08:24 -0700)
commit	1a0e5dbd3723e1194cc549def69fe7b557d4c72b
tree	6dc387216e93b22faaeb1ced56ce0b00b40aad8d	tree \| snapshot
parent	6f4eea90465ad0cd5f3d041b9b2c728426f2b8d4	commit \| diff

riscv: sifive: Add SiFive alternative ports

Add required ports of the Alternative scheme for SiFive.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

arch/riscv/Kconfig.erratas		diff \| blob \| history
arch/riscv/Kconfig.socs		diff \| blob \| history
arch/riscv/errata/Makefile		diff \| blob \| history
arch/riscv/errata/alternative.c		diff \| blob \| history
arch/riscv/errata/sifive/Makefile	[new file with mode: 0644]	blob
arch/riscv/errata/sifive/errata.c	[new file with mode: 0644]	blob
arch/riscv/include/asm/alternative.h		diff \| blob \| history

This is a test repository.

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