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[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)
authorVedant Kumar <vsk@apple.com>
Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)
committerVedant Kumar <vsk@apple.com>
Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)
commit1ae0aae5523207826cb7d137c6b9c54de4bc4d30
tree9d22f0a8560db3f8f17fe8e5e5a2692844e71a7e
parentcad24a07046c972c33ae9945bb2439b621aa45ca
[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)

The logic for this combine is almost identical to the logic for a
(sext (sextload x)) combine.

This commit factors out the logic so it can be shared by both combines,
and corrects the SDLoc assigned in the zext version of the combine.

Prior to this patch, for the given test case, we would apply the
location associated with the udiv instruction to instructions which
perform the load.

Part of: llvm.org/PR37262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331303 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/ARM/fold-zext-zextload.ll [new file with mode: 0644]
test/CodeGen/X86/h-registers-1.ll