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clk: samsung: Add compile time PLL rate validators
authorAndrzej Hajda <a.hajda@samsung.com>
Tue, 20 Feb 2018 07:05:39 +0000 (08:05 +0100)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Fri, 23 Feb 2018 14:15:20 +0000 (15:15 +0100)
commit1d5013f1b64dbd692975be5db0e42bac291c6de9
tree2350d997075252d6895efe1541ad27274cd7b776
parent179db533c08431f509a3823077549773d519358b
clk: samsung: Add compile time PLL rate validators

Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. To avoid possible mistakes we can use compile
time validation.
The patch introduces such validators and expands all initializers
with additional input frequency parameter, required to validate rates.
Since S3C24xx PLLs requires different validators two new macros have
been introduced to deal with it. Also, since PLLs 4502 and 4508 have
different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE.

As the patch adds only compile time validators it should not have impact
on compiled code.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos3250.c
drivers/clk/samsung/clk-exynos4.c
drivers/clk/samsung/clk-exynos5250.c
drivers/clk/samsung/clk-exynos5260.c
drivers/clk/samsung/clk-exynos5410.c
drivers/clk/samsung/clk-exynos5420.c
drivers/clk/samsung/clk-exynos5433.c
drivers/clk/samsung/clk-exynos7.c
drivers/clk/samsung/clk-pll.h
drivers/clk/samsung/clk-s3c2410.c