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(parent: 9e2d528) | patch
dwc3: core: clear DELAYP1TRANS with USB3PIPECTL register
authorMayank Rana <mrana@codeaurora.org>
Thu, 8 Sep 2016 18:09:37 +0000 (11:09 -0700)
committerMayank Rana <mrana@codeaurora.org>
Wed, 21 Sep 2016 16:12:06 +0000 (09:12 -0700)
commit1fdef7ce530009a509815ffcfbf108bc57a4de92
tree8df48a1172215a52a854bcf0d30f01190255941btree | snapshot
parent9e2d528dc47d04e98c5e6f1c4ef84fc268115d36commit | diff
dwc3: core: clear DELAYP1TRANS with USB3PIPECTL register

Commit fd115e68971b ("dwc3: core: Don't perform controller and PHYs
soft reset") removed clearing DELAYP1TRANS. It is recommended to clear
DELAYP1TRANS bit with USB3PIPECTL register which controls USB
controller allowing USB QMP PHY low power transitions.

Change-Id: I54ba694f4c997bf5ecc540cee274e2cb07b77446
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
drivers/usb/dwc3/core.c diff | blob | history
Mirror: https://github.com/0ranko0P/kernel_xiaomi_msm8998/
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