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(parent: 3c14505) | patch
clk: renesas: r8a77980: Fix RPC-IF module clock's parent
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thu, 7 Mar 2019 19:53:19 +0000 (22:53 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 2 Apr 2019 08:31:05 +0000 (10:31 +0200)
commit21ab095cbc069a351fa9cef919f2dafc43a8fde7
tree576eec4a8aacf56f1383d06154768ed6d3fcf293tree | snapshot
parent3c14505c68ca6b3b4d5258886e238f2a81729f06commit | diff
clk: renesas: r8a77980: Fix RPC-IF module clock's parent

Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...

Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a77980-cpg-mssr.c diff | blob | history
This is a test repository.
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