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spi: cadence-quadspi: Update the read timeout based on the length
authorSai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Mon, 20 Mar 2023 09:59:30 +0000 (15:29 +0530)
committerMark Brown <broonie@kernel.org>
Mon, 17 Apr 2023 17:16:38 +0000 (18:16 +0100)
commit22c8ce0aa274cea2ff538ffdf723053ecf77d78b
tree8de96cb4a7ad15ecd2518ae6fb45c36561d558ac
parent6d87552c0b86b9677d762002082df5f5b7e3c33f
spi: cadence-quadspi: Update the read timeout based on the length

When performing indirect read via external DMA the timeout for
completion is set equal to the read length instead of fixed timeout value.
For reads larger than 500 bytes, the timeout will continue to be
equal to the read length whereas for a small read like the Read Status
Register command, the timeout would be 1 or 2 milliseconds. This is not
enough to cover the overhead needed in setting up DMA, in that case make
sure the timeout is at least 500ms to allow DMA to finish. This solution
is inline with the timeout used for Direct read via DMA.

Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Link: https://lore.kernel.org/r/20230320095931.2651714-2-sai.krishna.potthuri@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-cadence-quadspi.c