[AArch64][SVE] Asm: Predicated floating point reductions.

[AArch64][SVE] Asm: Predicated floating point reductions.

This patch adds support for various floating-point
reduction operations:

  FADDA    strictly-ordered add reduction, accumulating in scalar
  FADDV    recursive add reduction to scalar
  FMAXV    recursive max reduction to scalar
  FMINV    recursive min reduction to scalar
  FMAXNMV  recursive max number reduction to scalar
  FMINNMV  recursive min number reduction to scalar

The reduction is predicated, e.g.

  fadda d0, p0, d0, z1.d

performs the add-reduction in strict order on active elements
in z1, accumulating into d0.

  faddv d0, p0, z1.d

performs the add-reduction (not in strict order)
on active elements in z1, storing the result in d0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338123 91177308-0d34-0410-b5e6-96231b3b80d8