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[AArch64] Improve single vector lane stores
authorEvandro Menezes <e.menezes@samsung.com>
Mon, 14 May 2018 15:26:35 +0000 (15:26 +0000)
committerEvandro Menezes <e.menezes@samsung.com>
Mon, 14 May 2018 15:26:35 +0000 (15:26 +0000)
commit29ab6ce3aab3402841eccc07228e8d4e96b62e3f
treedb6a7a91cb7296cd3897a26058c09619207decb9
parent40a24a84872af797f68bafa8fcbc61861d5db0e1
[AArch64] Improve single vector lane stores

When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead.

Differential revision: https://reviews.llvm.org/D46655

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332251 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64InstrInfo.td
test/CodeGen/AArch64/arm64-neon-copy.ll
test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
test/CodeGen/AArch64/arm64-st1.ll
test/CodeGen/AArch64/fp16-vector-load-store.ll