clk: samsung: exynos5250: Fix PLL rates
Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. If that is not the case, rate of the PLL's child clock
might be set not as expected. For instance, if in the PLL rates table we have
a
393216000 Hz entry and the real value as returned by the PLL's recalc_rate
callback is
393216003, after setting PLL's clk rate to
393216000 clk_get_rate
will return
393216003. If we now attempt to set rate of a PLL's child divider
clock to
393216000/2 its rate will be
131072001, rather than
196608000.
That is, the divider will be set to 3 instead of 2, because
393216003/2 is
greater than
196608000.
To fix this issue declared rates are changed to exactly match rates generated
by the PLL, as calculated from the P, M, S, K coefficients.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>