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clk: sunxi: A31: Fix wrong AHB gate number
authorAndre Przywara <andre.przywara@arm.com>
Wed, 23 Jan 2019 00:59:11 +0000 (00:59 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 23 Mar 2019 12:19:42 +0000 (13:19 +0100)
commit2c304e47c6ff8b1698fd7586488fc7d425f8b02c
tree7ec34b19c683718406ed06d7874c80b72baa506atree | snapshot
parent2e0e73d7b82e2432446f544d0492435146a0af37commit | diff
clk: sunxi: A31: Fix wrong AHB gate number

[ Upstream commit ee0b27a3a4da0b0ed2318aa092f8856896e9450b ]

According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/sunxi-ng/ccu-sun6i-a31.c diff | blob | history
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