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[globalisel] Update GlobalISel emitter to match new representation of extending loads
authorDaniel Sanders <daniel_l_sanders@apple.com>
Sat, 5 May 2018 20:53:24 +0000 (20:53 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Sat, 5 May 2018 20:53:24 +0000 (20:53 +0000)
commit2cc8a8f7a4bd2fee4da01cc4d25f373b023ec1ec
treefa30a8a76d6a45ea34d3e17ab7c40bc2b5b36a4a
parentb1f8c095b1590c9d5018c4381affc67a7ed914f9
[globalisel] Update GlobalISel emitter to match new representation of extending loads

Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
  registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
  extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
  improve optimization of extends and truncates, this legality requirement
  would spread without considerable care w.r.t when certain combines were
  permitted.
* The SelectionDAG importer required some ugly and fragile pattern
  rewriting to translate patterns into this style.

This patch changes the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

Each extending load can be lowered by the legalizer into separate extends
and loads, however a target that supports s1 will need the any-extending
load to extend to at least s8 since LLVM does not represent memory accesses
smaller than 8 bit. The legalizer can widenScalar G_LOAD into an
any-extending load but sign/zero-extending loads need help from something
else like a combiner pass. A follow-up patch that adds combiner helpers for
for this will follow.

The new representation requires that the MMO correctly reflect the memory
access so this has been corrected in a couple tests. I've also moved the
extending loads to their own tests since they are (mostly) separate opcodes
now. Additionally, the re-write appears to have invalidated two tests from
select-with-no-legality-check.mir since the matcher table no longer contains
loads that result in s1's and they aren't legal in AArch64 anymore.

Depends on D45540

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar

Reviewed By: rtereshin

Subscribers: javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45541

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331601 91177308-0d34-0410-b5e6-96231b3b80d8
17 files changed:
include/llvm/CodeGen/GlobalISel/InstructionSelector.h
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
include/llvm/Target/GlobalISel/SelectionDAGCompat.td
lib/Target/AArch64/AArch64InstructionSelector.cpp
lib/Target/AArch64/AArch64LegalizerInfo.cpp
test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
test/CodeGen/AArch64/GlobalISel/select-extload.mir [new file with mode: 0644]
test/CodeGen/AArch64/GlobalISel/select-load.mir
test/CodeGen/AArch64/GlobalISel/select-sextload.mir [new file with mode: 0644]
test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
test/CodeGen/AArch64/GlobalISel/select-zextload.mir [new file with mode: 0644]
test/TableGen/GlobalISelEmitter.td
utils/TableGen/GlobalISelEmitter.cpp