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net: axienet: increase default TX ring size to 128
authorRobert Hancock <robert.hancock@calian.com>
Tue, 18 Jan 2022 21:41:32 +0000 (15:41 -0600)
committerDavid S. Miller <davem@davemloft.net>
Wed, 19 Jan 2022 11:29:14 +0000 (11:29 +0000)
commit2d19c3fd80178160dd505ccd7fed1643831227a5
tree5e43d89d4f58a4f78e4feaca881789e8c8ea0be6
parentbb193e3db8b86a63f26889c99e14fd30c9ebd72a
net: axienet: increase default TX ring size to 128

With previous changes to make the driver handle the TX ring size more
correctly, the default TX ring size of 64 appears to significantly
bottleneck TX performance to around 600 Mbps on a 1 Gbps link on ZynqMP.
Increasing this to 128 seems to bring performance up to near line rate and
shouldn't cause excess bufferbloat (this driver doesn't yet support modern
byte-based queue management).

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/xilinx/xilinx_axienet_main.c