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ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
authorMarek Vasut <marex@denx.de>
Fri, 28 Jun 2019 00:19:44 +0000 (02:19 +0200)
committerDinh Nguyen <dinguyen@kernel.org>
Tue, 30 Jul 2019 14:05:45 +0000 (09:05 -0500)
commit2dbaa6a6dcf01b84bcf076a0e906dc7dacbd0a1d
tree810ac9fd567f05b8a6016d2d0bf7c7a1cdc557f3tree | snapshot
parent325ec920eeb7b96b9cb490213bfdb03650c19d86commit | diff
ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA

Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts diff | blob | history
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