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Generic Bypass Slow Div
authorPreston Gurd <preston.gurd@intel.com>
Tue, 4 Sep 2012 18:22:17 +0000 (18:22 +0000)
committerPreston Gurd <preston.gurd@intel.com>
Tue, 4 Sep 2012 18:22:17 +0000 (18:22 +0000)
commit2e2efd960056bbb7e4bbd843c8de55116d52aa7d
tree664f06659d0c01493523f47689a78ec7199dcce3
parente20cf3d14997c3511e264748c59687a801caa6ed
Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder,  or both.

Patch by Tyler Nowicki!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/Target/TargetLowering.h
include/llvm/Transforms/Utils/BypassSlowDivision.h [new file with mode: 0644]
lib/CodeGen/SelectionDAG/TargetLowering.cpp
lib/Target/X86/X86.td
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86Subtarget.cpp
lib/Target/X86/X86Subtarget.h
lib/Transforms/Scalar/CodeGenPrepare.cpp
lib/Transforms/Utils/BypassSlowDivision.cpp [new file with mode: 0644]
lib/Transforms/Utils/CMakeLists.txt
test/CodeGen/X86/atom-bypass-slow-division.ll [new file with mode: 0644]