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drm/i915: Estimate and update missed vblanks.
authorDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Sat, 3 Feb 2018 05:13:02 +0000 (21:13 -0800)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 15 Feb 2018 19:50:22 +0000 (11:50 -0800)
commit2e8bf223d8f51ffe98f7bc11522939e62ab79a55
tree6f9c820a130e1db40432f59e7bc00fe4aafcfe6c
parentd0bb96b4be69feea97f16de5306c35e280658931
drm/i915: Estimate and update missed vblanks.

The frame counter may have got reset between disabling and enabling vblank
interrupts due to DMC putting the hardware to DC5/6 states if PSR was
active. The frame counter could also have stalled if PSR was active in case
there was no DMC. The frame counter resetting has a user visible impact
of screen freezes.

Make use of drm_vblank_restore() to compute missed vblanks for the duration
in which vblank interrupts were disabled and update the vblank counter with
this value as diff. There's no need to check if PSR was actually active in
the interrupt disabled duration, so simplify the check to a feature check.

Enabling vblank interrupts wakes up the hardware from DC5/6 and prevents it
from going back again as long as the there are pending interrupts. So, we
don't have to explicity disallow DC5/6 after enabling vblank interrupts to
keep the counter running.

This change is not applicable to CHV, as enabling interrupts does not
prevent the hardware from activating PSR.

v2: Added comments(Rodrigo) and rewrote commit message.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180203051302.9974-10-dhinakaran.pandiyan@intel.com
drivers/gpu/drm/i915/i915_irq.c