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[ARM] Replace fp-only-sp and d16 with fp64 and d32.
authorSimon Tatham <simon.tatham@arm.com>
Tue, 28 May 2019 16:13:20 +0000 (16:13 +0000)
committerSimon Tatham <simon.tatham@arm.com>
Tue, 28 May 2019 16:13:20 +0000 (16:13 +0000)
commit2edda5220da6d627835088ddd969b20b563cae88
treedfe411fbf46f6b45d8c201f85bcf15a21f5e9260
parent6e90aeea9bf4b1904c942a7171a49d0c3569d391
[ARM] Replace fp-only-sp and d16 with fp64 and d32.

Those two subtarget features were awkward because their semantics are
reversed: each one indicates the _lack_ of support for something in
the architecture, rather than the presence. As a consequence, you
don't get the behavior you want if you combine two sets of feature
bits.

Each SubtargetFeature for an FP architecture version now comes in four
versions, one for each combination of those options. So you can still
say (for example) '+vfp2' in a feature string and it will mean what
it's always meant, but there's a new string '+vfp2d16sp' meaning the
version without those extra options.

A lot of this change is just mechanically replacing positive checks
for the old features with negative checks for the new ones. But one
more interesting change is that I've rearranged getFPUFeatures() so
that the main FPU feature is appended to the output list *before*
rather than after the features derived from the Restriction field, so
that -fp64 and -d32 can override defaults added by the main feature.

Reviewers: dmgreen, samparker, SjoerdMeijer

Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D60691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361845 91177308-0d34-0410-b5e6-96231b3b80d8
45 files changed:
include/llvm/MC/MCSubtargetInfo.h
lib/MC/MCSubtargetInfo.cpp
lib/Object/ELFObjectFile.cpp
lib/Support/ARMTargetParser.cpp
lib/Target/ARM/ARM.td
lib/Target/ARM/ARMAsmPrinter.cpp
lib/Target/ARM/ARMBaseInstrInfo.cpp
lib/Target/ARM/ARMBaseRegisterInfo.cpp
lib/Target/ARM/ARMFastISel.cpp
lib/Target/ARM/ARMISelDAGToDAG.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMInstrInfo.td
lib/Target/ARM/ARMInstructionSelector.cpp
lib/Target/ARM/ARMLegalizerInfo.cpp
lib/Target/ARM/ARMRegisterBankInfo.cpp
lib/Target/ARM/ARMSubtarget.h
lib/Target/ARM/ARMTargetTransformInfo.h
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
test/CodeGen/ARM/arm-storebytesmerge.ll
test/CodeGen/ARM/arm32-rounding.ll
test/CodeGen/ARM/build-attributes.ll
test/CodeGen/ARM/fast-isel-call.ll
test/CodeGen/ARM/float-helpers.s
test/CodeGen/ARM/fp-only-sp.ll
test/CodeGen/ARM/fp16-instructions.ll
test/CodeGen/ARM/fp16-promote.ll
test/CodeGen/ARM/fpconv.ll
test/CodeGen/ARM/half.ll
test/CodeGen/ARM/inlineasm-X-allocation.ll
test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
test/CodeGen/ARM/no-fpu.ll
test/CodeGen/Thumb2/aapcs.ll
test/CodeGen/Thumb2/float-intrinsics-double.ll
test/CodeGen/Thumb2/float-intrinsics-float.ll
test/CodeGen/Thumb2/t2sizereduction.mir
test/MC/ARM/armv8.3a-js.s
test/MC/ARM/d16.s
test/MC/ARM/invalid-neon-v8.s
test/MC/ARM/single-precision-fp.s
test/MC/ARM/vldm-vstm-diags.s
test/Transforms/Inline/ARM/inline-fp.ll
test/Transforms/LoopUnroll/runtime-epilog-debuginfo.ll