[PowerPC] avoid redundant analysis while lowering an immediate; NFC

[PowerPC] avoid redundant analysis while lowering an immediate; NFC

This patch reduces compilation time by avoiding redundant analysis while selecting instructions to create an immediate.
If the instruction count required to create the input number without rotate is 2, we do not need further analysis to find a shorter instruction sequence with rotate; rotate + load constant cannot be done by 1 instruction (i.e. getInt64CountDirectnever return 0).
This patch should not change functionality.

Differential Revision: https://reviews.llvm.org/D34986

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307623 91177308-0d34-0410-b5e6-96231b3b80d8