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PR19320:
authorStepan Dyatkovskiy <stpworld@narod.ru>
Thu, 3 Apr 2014 11:29:15 +0000 (11:29 +0000)
committerStepan Dyatkovskiy <stpworld@narod.ru>
Thu, 3 Apr 2014 11:29:15 +0000 (11:29 +0000)
commit37e5cfa4aae0dd693ab0c35ff78d37f5ddfe177d
treeb8f393497bcc07da41faf2778697ccc041520ac8tree | snapshot
parent3f11cd0d25971e2f8231a74a27339146d786644dcommit | diff
PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/AsmParser/ARMAsmParser.cpp diff | blob | history
test/MC/ARM/ldrd-strd-gnu-sp.s [new file with mode: 0644] blob
external/llvm
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