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target/riscv: machine: Add debug state description
authorBin Meng <bin.meng@windriver.com>
Thu, 21 Apr 2022 00:33:22 +0000 (08:33 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 22 Apr 2022 00:35:16 +0000 (10:35 +1000)
commit38b4e781a4281ee4b2f3ef1bddb432f2ce6d5af6
treefc87222b3ea4d2fc4f30183b2b9db089708eef46tree | snapshot
parentb6092544fcbe747c005db25c38d8081d281c79adcommit | diff
target/riscv: machine: Add debug state description

Add a subsection to machine.c to migrate debug CSR state.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-5-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/machine.c diff | blob | history
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