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R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
authorTom Stellard <thomas.stellard@amd.com>
Wed, 14 Aug 2013 23:24:32 +0000 (23:24 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Wed, 14 Aug 2013 23:24:32 +0000 (23:24 +0000)
commit38d5e1c36d954f1ff6489f58efd1d4865217cf9b
tree451454dd8bf6ea5ec2f3ea021da2c7f6de4a928a
parent636298ba64fd07d4ddcae6005e7fc1db43eb5335
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2

Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.

v2:
  - Use an SGPR register class if all the operands of BUILD_VECTOR are
    SGPRs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
lib/Target/R600/AMDGPUInstructions.td
lib/Target/R600/AMDGPURegisterInfo.cpp
lib/Target/R600/AMDGPURegisterInfo.h
lib/Target/R600/R600RegisterInfo.cpp
lib/Target/R600/R600RegisterInfo.h
lib/Target/R600/SIInstructions.td
test/CodeGen/R600/si-lod-bias.ll [new file with mode: 0644]
test/CodeGen/R600/store.ll