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(parent: 920a1f9) | patch
target/riscv: rvb: add/shift with prefix zero-extend
authorKito Cheng <kito.cheng@sifive.com>
Wed, 5 May 2021 16:06:16 +0000 (00:06 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 7 Jun 2021 23:59:45 +0000 (09:59 +1000)
commit3a4a43e4e213a18d1ee4ed97090a5e86401c85bc
tree49772d3c0585632261e495a7bb054ab064781c0dtree | snapshot
parent920a1f9955c528f2be3ff9c9e1cbf40ddad1b192commit | diff
target/riscv: rvb: add/shift with prefix zero-extend

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn32.decode diff | blob | history
target/riscv/insn_trans/trans_rvb.c.inc diff | blob | history
target/riscv/translate.c diff | blob | history
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