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[AMDGPU] Created a sub-register class for the return address operand in the return...
authorChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Tue, 9 Jul 2019 16:48:42 +0000 (16:48 +0000)
committerChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Tue, 9 Jul 2019 16:48:42 +0000 (16:48 +0000)
commit3b296991561d61e9a1be2c01a094d006d1918780
tree81c892becf572f3698f66264b5c04671616c33f0
parenta3d9e32efb06a97baef1e377aa7bdfc426ce60bb
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.

Function return instruction lowering, currently uses the fixed register pair s[30:31] for holding
the return address. It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class
exclusive of the CSRs, and used this regclass while lowering the return instruction.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D63924

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365512 91177308-0d34-0410-b5e6-96231b3b80d8
14 files changed:
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIRegisterInfo.td
lib/Target/AMDGPU/SOPInstructions.td
test/CodeGen/AMDGPU/call-graph-register-usage.ll
test/CodeGen/AMDGPU/call-preserved-registers.ll
test/CodeGen/AMDGPU/callee-frame-setup.ll
test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
test/CodeGen/AMDGPU/chain-hi-to-lo.ll
test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
test/CodeGen/AMDGPU/llvm.log.f16.ll
test/CodeGen/AMDGPU/llvm.log10.f16.ll
test/CodeGen/AMDGPU/load-lo16.ll
test/CodeGen/AMDGPU/nested-calls.ll
test/CodeGen/AMDGPU/wave32.ll