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[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 19 Jun 2019 18:00:24 +0000 (18:00 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 19 Jun 2019 18:00:24 +0000 (18:00 +0000)
commit3bf67713b28e8d86affbc800c370cac205614250
tree4aa5941993b8659ef896e7e038cd99c951275c35
parent8de78e2cc4fdfae95648855ccfdd8f29c89c2d19
[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG

Simplify ZERO_EXTEND_VECTOR_INREG if the extended bits are not required.

Matches what we already do for ZERO_EXTEND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363850 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/TargetLowering.cpp
test/CodeGen/X86/combine-pmuldq.ll
test/CodeGen/X86/pmul.ll
test/CodeGen/X86/vector-reduce-mul-widen.ll
test/CodeGen/X86/vector-reduce-mul.ll