git.osdn.net Git - android-x86/external-llvm.git/commit

(root) / android-x86 / external-llvm.git / commit

author	Quentin Colombet <qcolombet@apple.com>
	Wed, 13 Jul 2016 20:36:03 +0000 (20:36 +0000)
committer	Quentin Colombet <qcolombet@apple.com>
	Wed, 13 Jul 2016 20:36:03 +0000 (20:36 +0000)
commit	3d35f0d482cf5ce6cf87d10a108ade79e7cc2065
tree	6edf6c332fb43c5abd56df3de9ad8a2097a50aba	tree \| snapshot
parent	2b1c1c15c8fbacf7c9f46398a5850104ee3317a3	commit \| diff

[MIR] Print on the given output instead of stderr.

Currently the MIR framework prints all its outputs (errors and actual
representation) on stderr.

This patch fixes that by printing the regular output in the output
specified with -o.

Differential Revision: http://reviews.llvm.org/D22251

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275314 91177308-0d34-0410-b5e6-96231b3b80d8

100 files changed:

lib/CodeGen/LLVMTargetMachine.cpp		diff \| blob \| history
test/CodeGen/AArch64/branch-folder-merge-mmos.ll		diff \| blob \| history
test/CodeGen/AArch64/stackmap-frame-setup.ll		diff \| blob \| history
test/CodeGen/AMDGPU/detect-dead-lanes.mir		diff \| blob \| history
test/CodeGen/AMDGPU/indirect-addressing-undef.mir		diff \| blob \| history
test/CodeGen/AMDGPU/rename-independent-subregs.mir		diff \| blob \| history
test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll		diff \| blob \| history
test/CodeGen/ARM/thumb1-ldst-opt.ll		diff \| blob \| history
test/CodeGen/MIR/AArch64/cfi-def-cfa.mir		diff \| blob \| history
test/CodeGen/MIR/AArch64/machine-dead-copy.mir		diff \| blob \| history
test/CodeGen/MIR/AArch64/machine-scheduler.mir		diff \| blob \| history
test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir		diff \| blob \| history
test/CodeGen/MIR/AArch64/stack-object-local-offset.mir		diff \| blob \| history
test/CodeGen/MIR/AArch64/target-flags.mir		diff \| blob \| history
test/CodeGen/MIR/AMDGPU/target-index-operands.mir		diff \| blob \| history
test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir		diff \| blob \| history
test/CodeGen/MIR/ARM/bundled-instructions.mir		diff \| blob \| history
test/CodeGen/MIR/ARM/cfi-same-value.mir		diff \| blob \| history
test/CodeGen/MIR/ARM/imm-peephole-arm.mir		diff \| blob \| history
test/CodeGen/MIR/ARM/imm-peephole-thumb.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/basic-blocks.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/frame-info.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/llvmIR.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/llvmIRMissing.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/machine-function.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/multiRunPass.mir		diff \| blob \| history
test/CodeGen/MIR/Generic/register-info.mir		diff \| blob \| history
test/CodeGen/MIR/Hexagon/anti-dep-partial.mir		diff \| blob \| history
test/CodeGen/MIR/Lanai/peephole-compare.mir		diff \| blob \| history
test/CodeGen/MIR/Mips/memory-operands.mir		diff \| blob \| history
test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir		diff \| blob \| history
test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir		diff \| blob \| history
test/CodeGen/MIR/X86/basic-block-liveins.mir		diff \| blob \| history
test/CodeGen/MIR/X86/block-address-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/callee-saved-info.mir		diff \| blob \| history
test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir		diff \| blob \| history
test/CodeGen/MIR/X86/cfi-def-cfa-register.mir		diff \| blob \| history
test/CodeGen/MIR/X86/cfi-offset.mir		diff \| blob \| history
test/CodeGen/MIR/X86/constant-pool.mir		diff \| blob \| history
test/CodeGen/MIR/X86/dead-register-flag.mir		diff \| blob \| history
test/CodeGen/MIR/X86/early-clobber-register-flag.mir		diff \| blob \| history
test/CodeGen/MIR/X86/external-symbol-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/fixed-stack-objects.mir		diff \| blob \| history
test/CodeGen/MIR/X86/frame-info-save-restore-points.mir		diff \| blob \| history
test/CodeGen/MIR/X86/frame-info-stack-references.mir		diff \| blob \| history
test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir		diff \| blob \| history
test/CodeGen/MIR/X86/function-liveins.mir		diff \| blob \| history
test/CodeGen/MIR/X86/generic-virtual-registers.mir		diff \| blob \| history
test/CodeGen/MIR/X86/global-value-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/immediate-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/implicit-register-flag.mir		diff \| blob \| history
test/CodeGen/MIR/X86/inline-asm-registers.mir		diff \| blob \| history
test/CodeGen/MIR/X86/instructions-debug-location.mir		diff \| blob \| history
test/CodeGen/MIR/X86/jump-table-info.mir		diff \| blob \| history
test/CodeGen/MIR/X86/killed-register-flag.mir		diff \| blob \| history
test/CodeGen/MIR/X86/liveout-register-mask.mir		diff \| blob \| history
test/CodeGen/MIR/X86/machine-basic-block-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/machine-instructions.mir		diff \| blob \| history
test/CodeGen/MIR/X86/memory-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/metadata-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/named-registers.mir		diff \| blob \| history
test/CodeGen/MIR/X86/newline-handling.mir		diff \| blob \| history
test/CodeGen/MIR/X86/null-register-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/register-mask-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/simple-register-allocation-hints.mir		diff \| blob \| history
test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir		diff \| blob \| history
test/CodeGen/MIR/X86/stack-object-debug-info.mir		diff \| blob \| history
test/CodeGen/MIR/X86/stack-object-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/stack-objects.mir		diff \| blob \| history
test/CodeGen/MIR/X86/subregister-index-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/subregister-operands.mir		diff \| blob \| history
test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir		diff \| blob \| history
test/CodeGen/MIR/X86/successor-basic-blocks.mir		diff \| blob \| history
test/CodeGen/MIR/X86/undef-register-flag.mir		diff \| blob \| history
test/CodeGen/MIR/X86/used-physical-register-info.mir		diff \| blob \| history
test/CodeGen/MIR/X86/variable-sized-stack-objects.mir		diff \| blob \| history
test/CodeGen/MIR/X86/virtual-registers.mir		diff \| blob \| history
test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir		diff \| blob \| history
test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir		diff \| blob \| history
test/CodeGen/PowerPC/stackmap-frame-setup.ll		diff \| blob \| history
test/CodeGen/X86/eflags-copy-expansion.mir		diff \| blob \| history
test/CodeGen/X86/expand-vr64-gr64-copy.mir		diff \| blob \| history
test/CodeGen/X86/fixup-bw-copy.mir		diff \| blob \| history
test/CodeGen/X86/implicit-null-checks.mir		diff \| blob \| history
test/CodeGen/X86/machine-combiner-int.ll		diff \| blob \| history
test/CodeGen/X86/machine-copy-prop.mir		diff \| blob \| history
test/CodeGen/X86/patchpoint-verifiable.mir		diff \| blob \| history
test/CodeGen/X86/pr27681.mir		diff \| blob \| history
test/CodeGen/X86/stackmap-frame-setup.ll		diff \| blob \| history
test/CodeGen/X86/update-terminator.mir		diff \| blob \| history
test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll		diff \| blob \| history
test/DebugInfo/MIR/X86/live-debug-values-3preds.mir		diff \| blob \| history
test/DebugInfo/MIR/X86/live-debug-values.mir		diff \| blob \| history
test/DebugInfo/X86/bbjoin.ll		diff \| blob \| history
test/DebugInfo/X86/float_const_loclist.ll		diff \| blob \| history
test/DebugInfo/X86/safestack-byval.ll		diff \| blob \| history
test/DebugInfo/X86/single-dbg_value.ll		diff \| blob \| history
tools/llc/llc.cpp		diff \| blob \| history

external/llvm

RSS Atom

About OSDN

Find Software

Develop Software

Help