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Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset
authorNirav Dave <niravd@google.com>
Wed, 5 Jul 2017 01:21:23 +0000 (01:21 +0000)
committerNirav Dave <niravd@google.com>
Wed, 5 Jul 2017 01:21:23 +0000 (01:21 +0000)
commit3f4f926b6a830a8555747288e7d2de0a983ef395
tree1dad349cdbf6c37f191a9e3cdbf5ed522e23d336
parente75c6758b9cc13dba37025e347242ce81395432e
Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset

Relanding after rewriting undef.ll test to avoid host-dependant
endianness.

As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using
generic checks. Also, propagate missing local handling from there to
BaseIndexOffset checks.

Tests of note:

  * test/CodeGen/X86/build-vector* - Improved.
  * test/CodeGen/BPF/undef.ll - Improved store alignment allows an
    additional store merge

  * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a
    case we already do not handle well. Here, the DAG is improved, but
    scheduling causes a code size degradation.

Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D34472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307114 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
test/CodeGen/BPF/undef.ll
test/CodeGen/MSP430/Inst16mm.ll
test/CodeGen/X86/bswap-wide-int.ll
test/CodeGen/X86/build-vector-128.ll
test/CodeGen/X86/build-vector-256.ll
test/CodeGen/X86/build-vector-512.ll
test/CodeGen/X86/clear_upper_vector_element_bits.ll
test/CodeGen/X86/wide-integer-cmp.ll