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author	Alex Bradbury <asb@lowrisc.org>
	Thu, 7 Dec 2017 10:46:23 +0000 (10:46 +0000)
committer	Alex Bradbury <asb@lowrisc.org>
	Thu, 7 Dec 2017 10:46:23 +0000 (10:46 +0000)
commit	42a025965e830f80f5148fa620750404ed71c266
tree	caea75662ee3bdf674240ecb0d207c53c9385952	tree \| snapshot
parent	fd11bc081304b8ca3bf7a657eb45af7a6a24246f	commit \| diff

[RISCV] MC layer support for the standard RV32D instruction set extension

As the FPR32 and FPR64 registers have the same names, use
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an
FPR64 when necessary. The rest of this patch is very similar to the RV32F
patch.

Differential Revision: https://reviews.llvm.org/D39895

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320023 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp		diff \| blob \| history
lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp		diff \| blob \| history
lib/Target/RISCV/RISCV.td		diff \| blob \| history
lib/Target/RISCV/RISCVInstrInfo.td		diff \| blob \| history
lib/Target/RISCV/RISCVInstrInfoD.td	[new file with mode: 0644]	blob
lib/Target/RISCV/RISCVRegisterInfo.td		diff \| blob \| history
lib/Target/RISCV/RISCVSubtarget.h		diff \| blob \| history
test/MC/RISCV/rv32d-invalid.s	[new file with mode: 0644]	blob
test/MC/RISCV/rv32d-valid.s	[new file with mode: 0644]	blob
test/MC/RISCV/rv32f-invalid.s		diff \| blob \| history

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