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(parent: 0071820) | patch
target/riscv: rvb: count leading/trailing zeros
authorKito Cheng <kito.cheng@sifive.com>
Wed, 5 May 2021 16:06:03 +0000 (00:06 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 7 Jun 2021 23:59:43 +0000 (09:59 +1000)
commit438240185a9456747b19a29290018316271a3762
tree61d4bf60b5f37ae5f813673155fa163265725af4tree | snapshot
parent00718208c127315d82f1f1f8383ef29bc478628ecommit | diff
target/riscv: rvb: count leading/trailing zeros

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h diff | blob | history
target/riscv/insn32.decode diff | blob | history
target/riscv/insn_trans/trans_rvb.c.inc [new file with mode: 0644] blob
target/riscv/translate.c diff | blob | history
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