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clk: meson: Add support for parameters for specific PLLs
authorNeil Armstrong <narmstrong@baylibre.com>
Wed, 22 Mar 2017 10:32:23 +0000 (11:32 +0100)
committerKevin Hilman <khilman@baylibre.com>
Tue, 4 Apr 2017 19:05:12 +0000 (12:05 -0700)
commit45fcbec70c084631dc430810dad14a7ece5000b8
tree38cad16aac51dc80c82d6dbc117c7e66db64df7f
parentfac9a55b66c9b266171b69e73818a18225c41626
clk: meson: Add support for parameters for specific PLLs

In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific
parameters in order to initialize and lock correctly.

This patch adds an optional PARAM table used to initialize the PLL to a
default value with it's parameters in order to achieve to desired frequency.

The GP0 PLL in GXBB, GXL/GXM also needs some tweaks in the initialization
steps, and these are exposed along the PARAM table.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-2-git-send-email-narmstrong@baylibre.com
drivers/clk/meson/clk-pll.c
drivers/clk/meson/clkc.h