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(parent: 1ad3f9b) | patch
target/riscv: Add Zihintpause support
authorDao Lu <daolu@rivosinc.com>
Mon, 25 Jul 2022 03:47:28 +0000 (20:47 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 7 Sep 2022 07:18:33 +0000 (09:18 +0200)
commit4696f0ab5c436ed53567ce6baec67c921d9b70ae
tree435b5069b3fb5f03bff74765763330893bc84f10tree | snapshot
parent1ad3f9bdc76c83b23d689a111d5a160c528ac8bacommit | diff
target/riscv: Add Zihintpause support

Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.

Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Dao Lu <daolu@rivosinc.com>
Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c diff | blob | history
target/riscv/cpu.h diff | blob | history
target/riscv/insn32.decode diff | blob | history
target/riscv/insn_trans/trans_rvi.c.inc diff | blob | history
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