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[AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors
authorLemonBoy <thatlemon@gmail.com>
Fri, 5 Mar 2021 15:01:45 +0000 (16:01 +0100)
committerTom Stellard <tstellar@redhat.com>
Tue, 9 Mar 2021 04:14:33 +0000 (20:14 -0800)
commit46a1b0655666e21c56fa79560e9baee87405d4f4
treecbe9ed5a1b17f009566b8e35a92eb607a9df856btree | snapshot
parentd24e102ba2665dc6cd467f467813fba9c8261133commit | diff
[AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

Expand the horizontal reduction during the instruction selection phase, but only if the target doesn't support the full fp16 instruction set.

Fixes https://bugs.llvm.org/show_bug.cgi?id=49401

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D97840

(cherry picked from commit 8725b24c6d4abaa97425e704652a13dacb35fe3f)
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll diff | blob | history
llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll diff | blob | history
external/llvm-project
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