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(parent: 17f7213) | patch
MIR: Freeze reserved regs after parsing everything
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 27 Mar 2019 16:12:26 +0000 (16:12 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 27 Mar 2019 16:12:26 +0000 (16:12 +0000)
commit47101319272c19d0b9987ebb569d8ff1cbbdeafc
treefcae2c79ab5ace128c3ae6a6eff56ca48d168194tree | snapshot
parent17f72131c2b75309ce6363c8416220bb3d041f2acommit | diff
MIR: Freeze reserved regs after parsing everything

The AMDGPU implementation of getReservedRegs depends on
MachineFunctionInfo fields that are parsed from the YAML section. This
was reserving the wrong register since it was setting the reserved
regs before parsing the correct one.

Some tests were relying on the default reserved set for the assumed
default calling convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357083 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/MIRParser/MIRParser.cpp diff | blob | history
test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir diff | blob | history
test/CodeGen/AMDGPU/endpgm-dce.mir diff | blob | history
test/CodeGen/AMDGPU/misched-killflags.mir diff | blob | history
test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir diff | blob | history
test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir [new file with mode: 0644] blob
external/llvm
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