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author	Andrew Trick <atrick@apple.com>
	Wed, 9 Jan 2013 03:36:49 +0000 (03:36 +0000)
committer	Andrew Trick <atrick@apple.com>
	Wed, 9 Jan 2013 03:36:49 +0000 (03:36 +0000)
commit	47579cf390c42e0577519e0a2b6044baece9df00
tree	2744c5de5c5c825a168a20f90b9e099d8feaaf88	tree \| snapshot
parent	2af949ddddfaf2feb4a446c754e09d2d8c207ce4	commit \| diff

MIsched: add an ILP window property to machine model.

This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8

external/llvm

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include/llvm/CodeGen/TargetSchedule.h		diff \| blob \| history
include/llvm/MC/MCSchedule.h		diff \| blob \| history
include/llvm/Target/TargetSchedule.td		diff \| blob \| history
lib/CodeGen/MachineScheduler.cpp		diff \| blob \| history
lib/Target/ARM/ARMScheduleA9.td		diff \| blob \| history
lib/Target/X86/X86Schedule.td		diff \| blob \| history
lib/Target/X86/X86ScheduleAtom.td		diff \| blob \| history
test/CodeGen/PowerPC/misched-inorder-latency.ll	[moved from test/CodeGen/ARM/misched-inorder-latency.ll with 59% similarity]	diff \| blob \| history
utils/TableGen/SubtargetEmitter.cpp		diff \| blob \| history