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target/riscv: Separate priv from mmu_idx
authorFei Wu <fei2.wu@intel.com>
Wed, 12 Apr 2023 11:43:14 +0000 (13:43 +0200)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 5 May 2023 00:49:50 +0000 (10:49 +1000)
commit47debc7280430cc7665af2cb70caa1a4325ca060
tree3315159183d799c8df59f16ae58fdb547767fa6c
parent4acaa133b1f7af1867ac9e98bacc75012e6c123a
target/riscv: Separate priv from mmu_idx

Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/insn_trans/trans_privileged.c.inc
target/riscv/insn_trans/trans_xthead.c.inc
target/riscv/translate.c