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(parent: 9a6ef18) | patch
hw/pci-bridge/cxl_root_port: Wire up AER
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Thu, 2 Mar 2023 13:37:04 +0000 (13:37 +0000)
committerMichael S. Tsirkin <mst@redhat.com>
Tue, 7 Mar 2023 17:39:00 +0000 (12:39 -0500)
commit47f0e7ab3272737c174ca68c03843e0d1996dc22
tree288cb05131c3a7d69d3bbec3e295bda0cedd2292tree | snapshot
parent9a6ef182c03eaa138bae553f0fbb5a123bef9a53commit | diff
hw/pci-bridge/cxl_root_port: Wire up AER

We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
hw/pci-bridge/cxl_root_port.c diff | blob | history
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