OSDN Git Service

(root) / sagit-ice-cold / kernel_xiaomi_msm8998.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 0645a62) | patch
ARM: dts: msm: Add qcom,dump-size entry for dumping CPU L1/L2 caches
authorPrasad Sodagudi <psodagud@codeaurora.org>
Tue, 28 Jul 2015 04:31:04 +0000 (10:01 +0530)
committerSrinivas Ramana <sramana@codeaurora.org>
Tue, 1 Nov 2016 12:32:29 +0000 (18:02 +0530)
commit488460b4152924659d24d4a8e7043ec4568a4738
tree808e29d18291d417eba85b62691d6e42296d14f5tree | snapshot
parent0645a625acf8a125df3e8867457eab9b20ba9f83commit | diff
ARM: dts: msm: Add qcom,dump-size entry for dumping CPU L1/L2 caches

Update arm cache documentation about qcom,dump-size to dump
the CPU L1/L2 caches in order to analyze data corruption.

Change-Id: Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Documentation/devicetree/bindings/arm/cache.txt diff | blob | history
Mirror: https://github.com/0ranko0P/kernel_xiaomi_msm8998/
About OSDN
Find Software
Develop Software
Help