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author	Xiang, Haihao <haihao.xiang@intel.com>
	Fri, 8 Sep 2017 08:42:26 +0000 (16:42 +0800)
committer	Xiang, Haihao <haihao.xiang@intel.com>
	Thu, 11 Jan 2018 00:25:16 +0000 (08:25 +0800)
commit	48c0460784124b7dc5adb409e8e4eb9d57562705
tree	b1937c2bab5ee0db7de13ac9155db41a2f203a92	tree \| snapshot
parent	468b09447847a044049bec5cccfaa3baf420effb	commit \| diff

Add support for VP8 encode on CNL

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: peng.chen <peng.c.chen@intel.com>

19 files changed:

configure.ac		diff \| blob \| history
src/Makefile.sources		diff \| blob \| history
src/gen10_encoder_vp8.c	[new file with mode: 0644]	blob
src/gen8_mfc.c		diff \| blob \| history
src/i965_device_info.c		diff \| blob \| history
src/i965_encoder_vp8.c		diff \| blob \| history
src/shaders/brc/Makefile.am		diff \| blob \| history
src/shaders/brc/cnl/Makefile.am	[new file with mode: 0644]	blob
src/shaders/brc/cnl/hme_downscale_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/hme_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_brc_init_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_brc_reset_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_brc_update_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_enc_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_enc_genx_1.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_enc_genx_2.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_intra_distortion_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_mpu_genx_0.g10b	[new file with mode: 0644]	blob
src/shaders/brc/cnl/vp8_tpu_genx_0.g10b	[new file with mode: 0644]	blob

hardware/intel/common/vaapi

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