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drm/i915/guc: New GuC interrupt register for Gen11
authorMichal Wajdeczko <michal.wajdeczko@intel.com>
Mon, 27 May 2019 18:36:04 +0000 (18:36 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 28 May 2019 09:07:10 +0000 (10:07 +0100)
commit4a1f9dc119163677427fe03231af3bb0bf5adb4b
treef3832983c4b1ccb9380c34234dacc68a439c285d
parentafac50928403360f481a965b9bbc97bbd06f789f
drm/i915/guc: New GuC interrupt register for Gen11

Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.

Bspec: 21043

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-9-michal.wajdeczko@intel.com
drivers/gpu/drm/i915/intel_guc.c
drivers/gpu/drm/i915/intel_guc_reg.h