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[Hexagon] Skip mux generation when predicate register is undefined
authorKrzysztof Parzyszek <kparzysz@codeaurora.org>
Thu, 8 Jun 2017 20:56:36 +0000 (20:56 +0000)
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>
Thu, 8 Jun 2017 20:56:36 +0000 (20:56 +0000)
commit4a3c57b63a85a1b3db4c141ea6d6edf13830f017
tree9d462f934dbce3662a8a5862ee78c19ae14ed03dtree | snapshot
parent8efab37a20de7f0c3d94689efbda825ef35b11a5commit | diff
[Hexagon] Skip mux generation when predicate register is undefined

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305014 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Hexagon/HexagonGenMux.cpp diff | blob | history
test/CodeGen/Hexagon/mux-undef.ll [new file with mode: 0644] blob
external/llvm
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